A smart method of optimizing the read/write current on PCM array

Abstract

A method for optimizing the read/write current on phase change memory array is proposed. A smart current adjustment circuit is designed to bi-directionally alter the internal read/write current. The best read/write condition based on arrays can be found through this adjustment approach. Example of a 2-dimensional shmoo test on a 16k-bit phase change array implemented in 0.13 µm CMOS technology is given. The resistance distribution can also be roughly obtained. This method, taking advantage of the peripheral circuit, provides statistical yield data on a variety of read/write current, thus offering reliable and helpful indicators for chip parameter setup and process optimization.