IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Timing margin enhancement technique for current mode interface
Takefumi YoshikawaMakoto Nagata
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2014 Volume 11 Issue 19 Pages 20140766

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Abstract

This paper presents a circuit technique to enhance a timing margin between internal data and clock by enlarging an eye opening of the internal data in a unique current mode transceiver [1]. This technique compensates a systematic timing offset of the internal data, which is caused by unbalanced transmission current. The test-chip exhibits 0.1UI (Unit Interval) improvement of the internal data eye opening without significant power penalty, and achieves stable data communication through 50% longer transmission lines compared to the previous work [1].

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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