2014 Volume 11 Issue 19 Pages 20140845
A fast and efficient automatic frequency calibration (AFC) technique suitable for high frequency PLLs is presented in this paper and a 10 GHz PLL using the proposed AFC circuit is designed in 65 nm CMOS technology. The fast AFC technique is achieved through a multi-phase clock sampling based algorithm which reduces comparison time of each calibration step to at least one reference cycle with small frequency resolution. A dual-mode frequency divider is proposed to save circuit cost for a high frequency multi-phase clock generator. The proposed divider generates 8-phase high frequency clock for the proposed AFC to reduce its calibration time. Simulation results demonstrate that the calibration time is less than 1.44 us for each output frequency. The proposed AFC circuit is competitive among published AFC techniques in calibration time, unit cycle frequency resolution, area cost and power dissipation.