IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL
Kyoung-Ho KimJun-Han BaeYoung-Hyun JunKee-Won Kwon
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2014 Volume 11 Issue 24 Pages 20140828

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Abstract

With a new phase-rotating phase locked loop (RPLL), a 5-Gbit/s quarter-rate clock and data recovery (CDR) circuit is presented in this brief. The RPLL employs a split-tuned architecture to decouple the tradeoff between RPLL bandwidth and power consumption. The uncertainty of phase interpolation due to the non-deterministic characteristics of the phase frequency detector (PFD) is eliminated by employing a PFD synchronizer (PFDS). Hence RPLL precisely performs seamless phase adjustment. The CDR, implemented in a digital 65 nm CMOS technology, shows 5.5-ps rms and 47.2-ps peak-to-peak jitter in the recovered clock and 10−12 bit error rate while consuming 10.3 mW from a 1.2-V supply.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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