2014 Volume 11 Issue 24 Pages 20141002
This paper presents a real-time hardware accelerator for single image haze removal using dark channel prior and guided filter on a FPGA chip. Single image haze removal using dark channel prior and guided filter is one of the state-of-art algorithms recently proposed. However, its large quantity of calculation limits its real-time processing ability. So, in this paper, we design a hardware accelerator based on FPGA implementation for single image haze removal, which takes full advantage of the powerful parallel processing ability of the hardware and the parallelism of the algorithm. To be exactly, 1) the dark channel calculation part and the atmospheric light calculation part of the algorithm are modified to reduce the quantity of computation; 2) two pipelines are applied in the guided filtering to speed up the processing; 3) in addition, fast mean filtering technique is used to accelerate the mean filtering, which is the main calculation of the guided filter, by avoiding redundant computation. To the best of our knowledge, this paper is also the first FPGA design for single image haze removal using dark channel prior and guided filtering. The design can achieve 13.74 ms at 100 MHz when processing a 720 × 576 image, and gives almost the same results as that of original algorithm.