Low-power sigma-delta modulator with half-sample delayed-input feedforward

Abstract

A new input feedforward sigma-delta modulator architecture is presented for the design of low-voltage low-power high-precision oversampling analog-to-digital conversion. A half-sample delay is added in the input feedforward path in combination with multi-bit quantization to reduce integrator output swing and relax timing constraints in the feedback path. This results in substantial reduction of power dissipation in both analog and digital circuits in the modulator. The proposed implementation shows that no additional circuitry is needed to realize the added half-sample delay, thereby not introducing circuit nonidealities and eliminating power and area overhead. To verify the effectiveness of the architecture, a second-order sigma-delta modulator was designed and simulated using macro-models and 0.18-µm CMOS devices. It achieves a dynamic range of 96 dB for a signal bandwidth of 312.5 kHz at a 40-MHz sampling rate, which corresponds to an oversampling ratio of 64.