IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations
Xi FanHoupeng ChenQian WangXi LiYiyun ZhangJiajun HuRong JinYifeng ChenZhitang Song
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2014 Volume 11 Issue 24 Pages 20141071

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Abstract

A 1K-bit phase change random access memory (PCRAM) with improved periphery circuits for better reliable operations has been successfully developed in 130 nm CMOS technology. A flexible write driver is proposed to provide a novel continuous step-down pulses by studying programming strategies while a reliable read circuit is designed by investigating the special transition characteristics of PCRAM, leading to an effective write operation and a non-destructive read operation without any additional changes of the storage states. In addition, a large sense margin has been achieved and the read results corresponding well with the write operations, which demonstrate the influences of technology variations have been considerably decreased with the proposed periphery circuits.

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© 2014 by The Institute of Electronics, Information and Communication Engineers
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