抄録
In this paper, a new method is proposed to reduce the power consumption and occupied area of successive-approximation register analog to digital converters (SAR ADCs). The proposed solution is based on pre-charged capacitor array consisting of identical unit capacitors. According to the new method, switching operations to determine the least significant bits are replaced by adding pre-charged capacitors to the main capacitor array. This method is applicable for binary-weighted capacitor arrays with different switching schemes. With the presented method, switching energy and the number of unit capacitors are reduced by at least 50%.
