A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

Abstract

This letter reports a column-parallel clock skew self-calibration circuit for time-resolved (TR) CMOS image sensors. In TR CMOS imagers, as the time resolution increases, the skew of gating clock between pixels becomes a difficult problem because the clock skew causes the reduction of measurable maximum range in particular pixels or unmeasurable pixels. To calibrate the skew in short time, a column-parallel skew self-calibration circuit based on two-stage delay line and a dual clock tree is proposed. The experimental results show that the skew calibration circuit successfully reduces the skew from 247 ps_rms to 25 ps_rms, and the calibration time is only 12 µs, which is much faster than the previous work.