PCRAM-aware cluster allocation algorithm for hybrid main memory hierarchy

Shunfen Li; Xiaogang Chen; Mi Zhou; Gezi Li; Yiyun Zhang; Zhitang Song

doi:10.1587/elex.12.20150115

LETTER

PCRAM-aware cluster allocation algorithm for hybrid main memory hierarchy

Shunfen Li, Xiaogang Chen, Mi Zhou, Gezi Li, Yiyun Zhang, Zhitang Song

Author information

Shunfen Li
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
Xiaogang Chen
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
Mi Zhou
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
Gezi Li
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
Yiyun Zhang
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
Zhitang Song
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences

Keywords: PCRAM, hybrid main memory hierarchy, buffer management, cluster

JOURNAL FREE ACCESS

2015 Volume 12 Issue 5 Pages 20150115

DOI https://doi.org/10.1587/elex.12.20150115

Browse “Advance online publication” version

Details

Abstract

Phase Change Random Access Memory (PCRAM) has several characteristics that make it a promising candidate for main memory. In this paper, the challenges involved in incorporating PCRAM into the main memory hierarchy of flash-based systems are explored, and a hybrid memory hierarchy consisting of PCRAM and DRAM for SSD is proposed. To reduce the write traffic of Flash, a buffer management scheme for the hybrid memory is implemented. The proposed scheme above is implemented on basis of Disksim platform. The simulation results indicate that the proposed buffer algorithm can decrease the number of random write and erase operations of the SSD and improve the average system response rate obviously.

Corresponding author

Register with J-STAGE for free!