抄録
A simple nonlinear PFD circuit designed to achieve reduced reference spur and faster acquisition process for a PLL is proposed in this paper. The proposed nonlinear PFD is found to offer higher gain, eliminate glitches at the output and reduce both dead zone and reset delay when compared with the operation of conventional linear PFD (CL-PFD) and conventional NL-PFD (CNL-PFD). The PLL acquisition time got reduced by 50% and 11.69% while the reference spur 45% and 38.6% with respect to the CL-PFD and CNL-PFD respectively. Reference spur of −72.2 dBc, lock time of 1.548 µs, area of 0.2 mm2 and power dissipation of 6.2 mW are obtained for the prototype PLL using Proposed NL-PFD designed with 180 nm CMOS process.
