IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers
Yang JinjiangGe WeiCao PengYang Jun
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JOURNALS FREE ACCESS

2016 Volume 13 Issue 11 Pages 20160138

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Abstract

A LUT with Hierarchical Structure (HS-LUT) is proposed in this paper to realize the unique nonlinear component, Substitution Box (S-box), of the block ciphers. Different types of S-boxes are analyzed and four important features of them are summarized. Then, custom 4R/1W memory is proposed as the storage unit of the reconfigurable S-box, and an example set of block ciphers is put forward to describe how to achieve a satisfactory structure of reconfigurable S-box. The proposed HS-LUT is applicable for different sets of ciphers and it is implemented under TSMC 40 nm CMOS technology to compare with similar work. The comparison result shows that the proposed HS-LUT gains 6.88% to 51.76% area efficiency improvement.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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