A digitally enhanced LDO voltage regulator for UHF RFID passive tags

Abstract

This work proposes a Digitally Enhanced Low-Drop Out Voltage Regulator (DE-LDO) for Ultra High Radio Frequency IDentification (UHF RFID) passive tags. The DE-LDO design approach is based on the Finite State Machine (FSM) nature of the tag Digital Control. Injecting part of the FSM unconsumed current into LDO loop to enhance transient response, a more flat output voltage is obtained. Chip measurements shows that DE-LDO consumes a quiescent current of 600 nA at 1.6 V, delivering an output current and voltage of 8 µA and 1.2 V; a 69.76% Power Efficiency (PE) is observed. Circuit design and fabrication were performed using 0.50 µm CMOS technology.