EDSU: Error detection and sampling unified flip-flop with ultra-low overhead

Abstract

EDAC (Error Detection and Correction) techniques guarantee PVT variation safety by dynamically fixing timing error instead of providing static margins. However, previous EDAC works introduce additional area, power and performance penalty, thus the benefit from timing margin eliminating is limited. In this paper, we propose a novel EDAC Flip-Flop, EDSU, with ultra-low area overhead and nearly zero performance penalty. EDSU utilizes only two more transistors than conventional D-Flip Flop and can correct timing error simultaneously with detection. The ultra-lightweight property can obviously reduce area overhead and clock load, thus improve the variation tolerance ability and energy efficiency. EDSU is implemented in a commercial processor at SMIC 40 nm technology to evaluate its benefits. Simulation result shows EDSU inserted system gains 12.5% more performance at fixed voltage, 25% more variation tolerance and 10.5% energy saving at fixed throughput than state-of-art EDAC work.