IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A MapReduce architecture for embedded multiprocessor system-on-chips
Hao XiaoHuajuan ZhangFen GeNing Wu
著者情報
ジャーナル フリー

2016 年 13 巻 2 号 p. 20151025

詳細
抄録
With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities, this paper presents a MapReduce-based multiprocessor system-on-chip (MPSoC) for providing efficient architectural supports to MapReduce parallel programming paradigm. We implement the proposed MPSoC in cycle-accurate SystemC and evaluate its performance using a set of representative MapReduce applications. Results show that the proposed MPSoC can achieve up to 2.1× overall performance improvement over the current general purpose multicore processors in typical MapReduce applications.
著者関連情報
© 2016 by The Institute of Electronics, Information and Communication Engineers
前の記事 次の記事
feedback
Top