A burst-mode clock and data recovery circuit with two symmetric quadrature VCO’s

Bum-Hee Choi; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang

doi:10.1587/elex.13.20161086

LETTER

A burst-mode clock and data recovery circuit with two symmetric quadrature VCO’s

Bum-Hee Choi, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang

著者情報

キーワード: burst-mode clock recovery, quadrature phase VCO, instantaneous phase locking, passive optical network (PON)

ジャーナルフリー

2016 年 13 巻 24 号 p. 20161086

DOI https://doi.org/10.1587/elex.13.20161086

Browse “Advance online publication” version

詳細

抄録

This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric quadrature phase VCO’s. The reduced loop locking time of less than 5 bits was achieved without any extra delay circuits which are added in conventional schemes for timing control. The proposed circuit is designed in 350 nm CMOS process and its feasibility has been proved successfully operating at 1.25 Gb/s.

責任著者(Corresponding author)

J-STAGEへの登録はこちら（無料）