IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding
Hong LiangHe WeifengHe GuanghuiMao Zhigang
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2016 Volume 13 Issue 6 Pages 20160019

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Abstract

High Efficiency Video Coding (HEVC) is the newest video coding standard beyond H.264/AVC. To more efficiently compress image frames, variable block size DCT/IDCT (from 4 × 4 to 32 × 32) as well as 4 × 4 DST/IDST is employed by HEVC. In this paper, a novel area-efficient IDCT/IDST architecture for Ultra-High Definition (UHD) video applications is proposed. To reduce hardware cost and improve throughput efficiency, a novel resource sharing scheme, a template-based constant multiplication structure and a transpose buffer structure are adopted. Experimental results show that the proposed architecture can address 8K × 4K (7680 × 4320, 30 fps) video sequences at 390 MHz with at least a 39.5% gate count savings. Consequently, the proposed architecture offers a cost-efficient solution for future UHD applications.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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