IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
VLSI architecture of a Kalman filter optimized for real-time applications
Ramón Chávez-BracamontesMarco A. Gurrola-NavarroHumberto J. Jiménez-FloresManuel Bandala-Sánchez
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2016 Volume 13 Issue 6 Pages 20160043

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Abstract

This paper presents a parametrized VLSI architecture for an n-state Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5 µm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70 K transistors. For a performance of 50 filter iterations/second, the chip requires a clock frequency of 200 KHz where a negligible power consumption of 1.1 mW is observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20 MHz.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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