IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits
Toshihiro TakahashiRyo NumaguchiYuki YamanashiNobuyuki Yoshikawa
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2016 Volume 13 Issue 6 Pages 20160074

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Abstract

We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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