Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

抄録

A resilient tracking circuit for suppressing the timing variation of SRAM sense amplifier enable (SAE) signal is proposed. Pipelined replica bitline technique is used to favour the desired design. Simulation results show that the cycle time is reduced by ∼27% owing to ∼70% reduction of the standard deviation of SAE at a 1.05 V supply voltage in 28 nm CMOS technology with four-stage pipeline.