抄録
This paper presents a newly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC). The novel switching method achieves zero power consumption in the first three conversion cycles. The combination of low-power monotonic and charge averaging switching method is utilized for the remaining cycles. Compared to the conventional solution, the proposed switching technique reduces the average switching energy and number of capacitors by 99.18% and 75% respectively. Additionally, the common mode voltage at the comparator input is in a limited variation (less than 1/8Vref).
