IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Multi-core architecture with asynchronous clocks to prevent power analysis attacks
Yuan DuYong YeWeiliang JingZhenhua LiXiaoyun LiZhitang SongBomy Chen
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2017 Volume 14 Issue 4 Pages 20161220

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Abstract

This paper proposes a multi-core architecture with asynchronous clocks to prevent power analysis attacks for the first time. The multi cores normally execute different tasks with default clocks, but will execute the cryptographic algorithm together with asynchronous clocks to foil the side channel attacks. The cryptographic algorithm is split into multi parts, each of which is executed simultaneously by one core. Security analysis and simulation results show that the differential power analysis (DPA) attack and correlation power analysis (CPA) attack fail on data encryption standard (DES) and advanced encryption standard (AES) with the proposed architecture.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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