A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS

抄録

This paper presents an 8-channel time-interleaved SAR ADC. A novel sampling structure is proposed to improve the input bandwidth which also avoids time-skew calibration. The comparator offset cancellation is achieved by body voltage adjustment using low-power charge pump. Each channel has its own on-chip reference buffer to stable reference voltage and correct gain mismatches. The prototype is fabricated in 1P6M 0.13 µm CMOS technology. At 400 MS/s, the ADC achieves an SNDR of 50.84 dB and 45.7 dB at 19.1 MHz and 451 MHz, respectively. It consumes 200 mW, resulting in FOM of 1.76 pJ/con-step.