Voltage-mode ultra-low power four quadrant multiplier using subthreshold PMOS

抄録

A voltage-mode ultra low power four quadrant analog multiplier using subthreshold PMOS is presented in this paper. PMOS substract cell and combiner cell operating in the subthreshold region are used to lower the voltage-mode multiplier power consumption. Simulation results of the multiplier demonstrate a linearity error of 0.8%, a maximum THD of 4%, a −3 dB bandwidth of 1.4 MHz, and a power consumption of 77 nW with 100 fF load capacitor at a supply voltage of 0.6 V using a TSMC 0.18 um CMOS process.