2017 Volume 14 Issue 8 Pages 20161279
This paper presents a 200-Mb/s to 3.2-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180 nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking and reduce the frequency acquisition time. A frequency band selector for wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 11-ps peak-to-peak jitter at 3 Gb/s and the frequency acquisition time of 11.8 µs.