IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Design of a clockless MSP430 core using mixed asynchronous design flow
Ziho ShinMyeong-Hoon OhJeong-Gun LeeHag Young KimYoung Woo Kim
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2017 Volume 14 Issue 8 Pages 20170162


There are various limitations on the supporting tools and design methodologies for the implementation of an asynchronous delay-insensitive model. In this paper, we propose a new design flow by exploiting a mixed model, which combines a bounded delay model and a delay-insensitive model. To develop the design flow, we use an asynchronous finite-state machine for the bounded delay model and the null convention logic for the delay-insensitive model. Further, we designed an MSP430 core to verify the proposed design flow and the results of simulation show that it exhibits a performance improvement of 30.34% over its synchronous counterpart.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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