A 4 GS/s 6-bit 4-2 segmented current-steering DAC with compact current cells

抄録

This paper presents a 6-bit 4 GS/s current-steering digital-to-analog converter (DAC) for wideband systems. The 4-2 segmented structure is adopted for glitch reduction, and a dynamic decoder is proposed to maintain low power consumption and small area. In order to improve the high-frequency dynamic linearity, the forward-bias technique is employed to reduce the device sizes, and a compact one-dimensional (1-D) current source unit is used to further minimize the parasitic capacitance. The DAC is fabricated in 40-nm low-leakage CMOS process and occupies the active area of 0.036 mm². Over the entire Nyquist range, measurement results show a spurious free dynamic range (SFDR) of >39 dB at 2 GS/s sampling rate and >29 dB at 4 GS/s, respectively. The DAC consumes 28 mW power from 1.1 V supply voltage.