A 0.6 V temperature-stable CMOS voltage reference circuit with sub-threshold voltage compensation technique

抄録

This paper presents a CMOS reference circuit which can work properly under the near-threshold voltage of 0.6 V. It is based on the temperature characteristic of NMOS&PMOS transistors in the sub-threshold region. The temperature curve of the NMOS quasi-PTAT current and the PMOS quasi-PTAT current can be adjusted to have the same slope factor. Thus a temperature-stable reference voltage can be achieved by subtracting the quasi-PTAT voltage generated by the NMOS and PMOS circuits. It can be used under the supply voltage of 0.6 V, under which a traditional bipolar-based band gap reference cannot work properly. The circuit is designed and implemented in SMIC 65 nm CMOS process. It provides a nominal reference voltage of 154 mV, a average temperature coefficient of 87 ppm/°C in [−10°C∼80°C] under a 0.6 V supply voltage. The total power consumption is 60 µW and the chip area is 345 um * 182 um.