A place-aware redundancy methodology for multi-cell upsets mitigation in NoC

抄録

With scaling technology node, increasing Multi-Cell Upsets (MCU) is dramatically challenging the reliable system design. Network on Chip (NoC) as the communication infrastructure in a many-core processor, is also suffering the serious MCU impacts. Therefore, a place-aware redundancy methodology is proposed to alleviate the MCU impacts on NoC via exploiting MCU correlation. The simulation results demonstrate that, compared with 50% error recovery of latest works, the proposed approach achieves up to 95.8% error recovery with even only 6.91% extra area cost.