LETTER
A 0.85 V, 4.9 ppm/°C inherent temperature compensated voltage reference with −82 dB PSRR
2018 年 15 巻 22 号 p. 20180957
詳細
2018 年 15 巻 22 号 p. 20180957
A novel high PSRR and inherent temperature compensated CMOS voltage reference is present. A resistorless self-biased current source (RLSBCS) is proposed, formed by a gate-source voltage division (GSVD) structure, to achieve a temperature compensated proportional threshold-voltage difference. Meanwhile, a self-cascode structure is adopted to further cancel the residual negative temperature dependence of proposed threshold-voltage difference. Besides, feedback and self-bias techniques are introduced to enhance PSRR. The temperature coefficient is 4.9 ppm/°C in the temperature range of −25°C to 75°C and PSRR at DC is −82 dB with a power consumption of 9.8 nW.
