An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

抄録

Among prior short paths padding algorithms, greedy heuristic based on the number of short paths had been proven to be area saving and fast. For ultra-low supply multi-voltage designs, however, delay buffers explode due to improper padding locations caused by unconsidered delay variations. To overcome this problem, we propose a new evaluation function “effectiveness” for greedy heuristic, to characterize the benefit of buffer insertion, thereby to optimize the allocation of padding delay and reduce buffer overhead. An improved algorithm to dynamically update slacks during delay assignment stage is also introduced. Experimental results show average area reduction of 91.6% compared to the prior method.