IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs
Jongsun KimSW Han
著者情報
ジャーナル フリー

2018 年 15 巻 7 号 p. 20180156

詳細
抄録

A new low-power, fast-lock duty-cycle corrector (DCC) circuit with a digital duty-cycle adjuster (DCA) for mobile LPDDR3/LPDDR4 DRAMs is presented. The proposed DCC utilizes a digital feedback delay element (DFDE) to achieve wide duty-cycle correction and operating frequency ranges with low power consumption and fast lock capability. To obtain fast locking time and high duty-cycle correction accuracy, a 6-bit successive approximation register (SAR) controller utilizing a hybrid search algorithm is adopted. The measured duty-cycle error is less than ±0.85% over a 30–70% input duty-cycle range at 0.2–1.5 GHz. The DCC, which is fabricated in a 0.13-µm CMOS process, dissipates only 1.9 mW at 1 GHz and occupies an area of 0.036 mm2.

著者関連情報
© 2018 by The Institute of Electronics, Information and Communication Engineers
前の記事 次の記事
feedback
Top