A resource and timing optimized PCIe DMA architecture using FPGA internal data buffer

Abstract

In this paper, we propose a resource and timing optimized PCIe DMA architecture using FPGA internal data buffer memory. Firstly, an optimized PCIe DMA control process is proposed, focusing on reducing the capacity of required data buffer memory in PCIe DMA, which is realized by fastening DMA completion response, optimizing DMA register configuration, and avoiding conflicts between multiple threads. Required data buffer memory capacity is reduced by 97.6% from 24.10 MB to 0.56 MB, making FPGA internal memory resource enough for DMA transmission. Secondly, timing failure problems in FPGA caused by large internal memory utilization as PCIe DMA data buffer are solved, realized by a timing-optimized FIFO structure and a low-delay FIFO control mechanism. FPGA memory resource utilization rate without timing failure is increased from 12.4% to 100%, ensuring the reliability of PCIe DMA data transmission. This paper expands the application of PCIe data transmission, reducing the cost and complexity of relevant circuit design.