LETTER
Low-latency semi-systolic architecture for multiplication over finite fields
2019 年 16 巻 10 号 p. 20190080
詳細
2019 年 16 巻 10 号 p. 20190080
In this letter, we propose a low-latency semi-systolic architecture for multiplication based on the shifted polynomial basis over finite fields. The proposed multiplier saves at least 49.9% time complexity and 23.7% area-time complexity as compared to the related multipliers. The proposed multiplier can be used as a core circuit for various applications.
