2019 年 16 巻 10 号 p. 20190170
This paper presents a 0.4-V continuous-time delta-sigma modulator for high-quality power-efficient audio applications. A new ultra-low voltage amplifier for high linearity and low power consumption is proposed by exploring class-AB topology with a novel local common-mode-feedback loop. A low VT self-body-biased PMOS switch is employed in feedback digital-to-analog converter to improve the linearity performance against PVT-induced on resistance variation, which avoids clock boosting that may harm long-term reliability. A simple and robust non-overlapping clock generation circuit is proposed for high SNDR performance of modulator at 0.4-V or below. Fabricated in a 130-nm CMOS process, the modulator achieves 90.2 dB signal-to-noise-plus-distortion ratio (SNDR) with 0.2 pJ/step Figure-of-Merit (FoM) over a 20-kHz signal bandwidth, outperforming the reported audio delta-sigma modulators operating at 0.5-V or below. Furthermore, the modulator can operate with a supply down to 0.34-V while achieving an 86.1 dB SNDR at 0.17 pJ/step.
