An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters

Abstract

An efficient background timing skew calibration algorithm is proposed in this article, which detects the sampling time mismatches in time-interleaving analog-to digital converter (TIADC) by estimating the skew-related errors with a reference channel and aligns the sampling edge of each sub-ADC to that of the reference channel by analog variable-delay lines in the negative feedback loop. Compared with conventional background calibration methods based on complex algorithms or serious input restrictions, the proposed technique detects timing skews by only negligible hardware consisting of simple digital blocks and is applicable for a wide range of input including completely random signals. The detailed theoretical analysis and sufficient simulated results revealed that this algorithm is not sensitive to some non-ideal components in actual circuits like mismatches between channels or jitters in clock circuits, which verifies the practicability and robustness of this method.