A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Abstract

A novel static single-phase clocked (SSPC) dual-edge triggered flip-flop (DET-FF) is proposed to allow energy-efficient operation with aggressive voltage scaling. By employing two static latches with a single-phase clock, contention and clock phase mismatch is avoided, which significantly improves tolerance to PVT variations. The post-layout simulation performed with 28 nm CMOS technology shows that the proposed SSPC DET-FF consumes less power and has significantly better power-performance trade off (PDP) than prior-art DET-FFs. Our Monte Carlo analysis also showed that its supply voltage can be aggressively scaled down to 0.3 V even with PVT variations.