An implementation of low latency address-mapping logic for SSD controllers

Abstract

Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.