By skillfully applying the voltage bias, we firstly observed radiation-enhanced channel length modulation (CLM) of main transistor in 130 nm partially-depleted SOI nMOSFETs. And we found the radiation-enhanced CLM under Pass-Gate bias is more severe than that under ON bias, which reveals that the radiation-induced positive trapped charges in buried oxide is more responsible for this effect. A partially full depletion model is used to interpret this effect. And a TCAD simulation was used to verify our model. Good agreement between simulation and experiment is demonstrated.
Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.
This paper proposes novel single event upset (SEU) failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. To automatically evaluate the SEU failure probability and identify all the critical elements in a processor, complementary fault injection methods based on logic circuit simulator and Perl script are proposed. These methods can be used to randomly inject faults into D flip-flops (DFFs) and various types of memory at the register transfer level (RTL) as well as to evaluate the vision processor performance. Based on the evaluation results, an accurate periodic scrubbing technique is proposed to increase the processor availability. The results denote that the peak availability of the processor over a period of one year can be improved from 18% to 99.9% after scrubbing the RISC program memory for a period of 104 s. Therefore, we can improve the fault-tolerance performance of a vision processor while avoiding unnecessary area and power costs using techniques ranging from evaluation to mitigation.
An interleaved balance charger for four series-connected batteries is proposed in this study. Each battery can be charged individually in the proposed charger for balance charging process. The charger is operated in the discontinuous conduction mode (DCM) for power factor correction (PFC). Two flyback and two buckboost converters are input parallel-connected and controlled with multi-phase interleaving technique. The input current ripple is then greatly reduced. Each flyback converter is used to convert the charging power from the grid to one corresponding battery. The two buckboost converters are output parallel-connected and followed by a dual output converter. Two batteries in the series-connected battery tank are charged by the dual output converter. Moreover, a passive lossless snubber is proposed to recover the leakage inductance energy in the flyback converters. A 500 W prototype is constructed and corresponding experiments are carried out. From the experimental results, it can be seen that the efficiency is improved by about 3% compared with the topology with common RCD snubbers. The measured power factor of the proposed charger is higher than 0.976.
The photonic generation of microwaves or millimeter waves using the beat note of two lightwaves is an attractive technique for fiber-wireless communication systems because it enables high-frequency selectivity over the entire radio-frequency region as well as high-speed phase control via electro-optic phase modulators. In this paper, we propose a novel phase control method with small phase drift that uses the polarization dependence of electro-optic phase modulators combined with a feedback-controlled birefringent polarization rotator. The high stability and ultrafast phase shift keying operation of an optically generated microwave signal are experimentally demonstrated.
We demonstrate a flexible and lossless baud-rate switching process of the Nyquist OTDM signals using a wavelength selective switch (WSS) equipped with 4 output ports for different time slots. We generate the Nyquist OTDM signals with different baud rates without using any static OTDM devices such as an optical circuit. The WSS-only configuration allows a flexible baud rate switching by changing the filter functions applied to the WSS. The proposed system can successfully switch among 40, 80 and 120-Gboud/s signals with a switching duration of 80 ms.
This paper presents a method for designing high-efficiency concurrent dual-band (DB) class-E power amplifier (PA) that operate above the theoretical maximum frequency (fmax). The excess output capacitances at the two desired frequencies can be compensated using the proposed output matching network without separate design of harmonic compensation network, thus the fundamental and harmonic impedances for DB optimum class-E operation are achieved above the fmax, considering the parasitics of the packaged transistor. For demonstration, the fabricated DB class-E PA using GaN HEMT features the maximum power-added efficiency (PAE) of 74.1% and 72.6% at 1.9 and 2.5 GHz, while the output power is 40.3 and 40.7 dBm, respectively.
This letter presents several antenna-coupled 2.58 THz direct detectors based on 55 nm standard CMOS process. Each detector consists of a patch antenna and a metal-oxide-semiconductor field-effect-transistor (MOSFET) with an asymmetric channel. We demon-strated four detectors with THz wave coupling into the source with different width ratios of drain and source, and found that the responsivity is proportional to its asymmetric ratio. The detectors’ output signal is amplified with a low noise amplifier and extracted with a lock-in amplifier. The measured results showed that 2.58 THz detectors has a maximum responsivity (RV) of 822.5 V/W, with a corresponding noise equivalent power (NEP) of 24.2 pW/Hz0.5.
A low-noise high-gain high-speed optical receiver is fabricated in 0.13-µm SiGe BiCMOS. The transimpedance amplifier incorporating a differential common-base shunt-feedback topology features isolation to input capacitance and high transimpedance limit. Specifically, a comprehensive analytical expression of the input-referred noise current power spectral density of the transimpedance amplifier is derived and investigated, which provides insights for noise optimization. Additionally, the linearity of intermediate stages is improved by a modified variable-gain amplifier operating with automatic gain control. The measured results show a low noise level of 14.5 , 31-GHz bandwidth, and the maximum 71-dBΩ transimpedance.
For radar target detection, the selection of the optimal constant false alarm rate (CFAR) detector usually relies on clutter distribution types. By integrating two types of Mean Level and log-t CFAR detectors, a reconfigurable hardware architecture is proposed and implemented on field programmable gate array (FPGA). It allows to switch a suitable detector for specific clutter distribution and configure the parameters including the number of reference and guard cells, the threshold factor, and the desired false alarm probability. Synthesis results reveal its advantages of occupying 18% less hardware resources than the architecture that naively integrates two types of detectors. According to the experimental results, the proposed architecture can perform a processing speed of 100 MHz and require only 83 microseconds for a clutter of 8192 samples.
An analysis model of snapback voltage for the base resistance controlled thyristor (BRT) is developed in this paper. It’s shown that, improving hole current flowing into P-base region is an important way to suppress snapback phenomenon during forward conducting state. Thus, a new BRT with a floating N-region in N-drift layer is proposed. In this new structure, the floating N-region introduces a hole potential barrier in parasitic PNP to prevent holes from being swept into cathode. Then, almost all of hole current flow into P-base to trigger latch-up effect and the parasitic PNP transistor is greatly suppressed. Thus, snapback is significantly suppressed. Numerical simulation results show that, when doping level and length of floating N-region are 8.0 × 1015 cm−3 and 5.0 µm, snapback-free can be realized, and pulse discharge performance and turn on characteristics are greatly improved meanwhile the high blocking capability is maintained.
A simple eye-opening monitor (EOM) system based on two dimensional (2-D) counter-value profile is designed. The proposed EOM can be applied to adaptive equalizer coefficient control for better bit error rate (BER) performance in the high-speed serial interface. Input data is sampled 2048 times with 32 different clock phases on 32 different decision threshold amplitudes to the clocked comparator and the sampled outputs of ‘1’ or ‘0’ are recorded in the designated counter. The counter values at each phase and decision threshold amplitude are compared with a reference of 1024 for eye-opening monitor. The estimated eye-diagram is displayed on the monitor. Through the estimated eye-diagram, the optimal sampling timing can also be determined. The chip for sampling data and gathering the counter value has been designed through 180-nm CMOS process and 86 mW including I/O block is consumed on 2 Gb/s data rate.
The letter presents a high-performance doubly balanced ring mixer (DBRM) fabricated by a 0.1 µm GaAs pHEMT process that achieves ultrawide radio-frequency (RF) and intermediate frequency (IF) bandwidths. A multiple-coupled-line Marchand balun is optimized to extend the RF bandwidth. A novel structure is designed to directly extract the IF current from the RF balun without an additional IF coupler. Due to the proposed IF extraction structure, the IF bandwidth is broadened with decreased complexity. The size of the whole chip including the probe GSG pads is 0.95 × 0.65 mm2. The measured results show that the conversion loss is 7.2–11.9 dB for the RF frequency range of 35–95 GHz with an LO power level of 14 dBm and a fixed IF frequency of 1 GHz. In addition, the conversion loss is better than 12 dB for the IF frequency range from DC to 30 GHz under a fixed LO frequency.