Design of a third-order delta-sigma TDC with error-feedback structure

抄録

A 1-1-1 MASH delta-sigma TDC with a simpler structure was designed using an error feedback structure. The proposed 1-1-1 MASH delta-sigma TDC modulator has a single subtractor without any explicit integrator. Each modulator stage is composed of a subtractor, digital-to-time converter, and a quantizer. The subtractor generates the timing difference between input signal interval and the feedback signal interval. The digital-to-time converter (DTC) adds or subtracts fixed delays depending on the subtractor output and the quantizer values. The proposed circuit was designed using a 180 nm CMOS process. The simulation results show a resolution of 2.07 ps and a valid bit count of 11.5 bits at a sampling frequency of 50 MHz. The area is 0.14 mm², and the power consumption is 1.34 mW.