Novel method to optimize the column random telegraph signal performance in CMOS image sensor

Abstract

We present a methodology to define and distinguish the column random telegraph noise (RTS) derived from column bitline bias and comparator input transistors only based on the digital output data of each pixel. Many test experiments were conducted on the CMOS image sensor (CIS) chips fabricated with Dongbu 0.13 um, 1P5M process technology. According to the experiments, the threshold voltage and the channel length of the transistors have a significant influence on the intensity of the column RTS. Large channel length and proper threshold voltage, 0.15 V to 0.3 V for most cases, mean a low level of column RTS.