An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

抄録

The non-ideal factors and error sources of segmented DAC for multi-channel large array CMOS image sensor are given. An improved precise segmented DAC using adaptive switching technology is proposed. This scheme has been verified on a 50mm×50mm large array CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The measurement results show that the DNL of DAC can be reduced from 33 LSBs of traditional structure to within 0.5LSB, and the large array sensor chip reaches a high intrinsic dynamic range of 75dB, a low FPN of 0.06%, and a low photo response non-uniformity of 1.5% respectively. Finally, a good raw image is taken by the prototype sensor.