Approximate adder design with simplified lower-part approximation

抄録

This letter presents a novel approximate adder that reduces energy and power consumption by leveraging a simplified lower-part approximation. The proposed scheme reduces hardware costs while providing an acceptable accuracy performance. Implemented in a 32-nm CMOS technology, the proposed adder achieves area and power reductions of 67% and 91%, respectively, compare to a conventional adder. In terms of energy, it improves the power-delay and energy-delay products by 13.1% and 17.0%, respectively, compared to the other approximate adders considered herein. In addition, when adopted in a digital image processing application, the proposed adder shows a very promising output quality compared to that produced by an exact adder while providing excellent energy efficiency.