Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

抄録

In this letter, a high-voltage p-channel Lateral Diffused Metal Oxide Semiconductor Transistor (pLDMOS) with self-biased accumulation layer is proposed. A poly-silicon layer is formed on the thin insulator layer, which locates at the surface of the P-drift region. During on-state, an automatically obtained negative voltage is applied on the poly-silicon to induce a hole accumulation layer at the surface of the P-drift region. Therefore, the specific on-resistance (R_on,sp) can be significantly reduced. Moreover, the permittivity of the gate insulator on the P-drift can be increased by selecting different insulator materials. Thus, the R_on,sp can be further reduced due to more holes being accumulated at the surface of the P-drift. The simulation results shows that the R_on,sp of the proposed pLDMOS can be dramatically reduced by 62.3% to 82.5% compared with that of the p-type Triple RESURF silicon limit. For the proposed pLDMOS, the transient Figure of Merit (FOM) is significantly improved by several to 10 times and the static Figure of Merit (FOM) is improved by several times compared with those of an Extended Gate pLDMOS (EG-pLDMOS) and a conventional pLDMOS.