Silicon neuron transistor based on CMOS negative differential resistance (NDR)

Abstract

Computer-science-oriented and neuroscience-oriented are two general approaches to developing Artificial General Intelligence (AGI). In this study, a silicon neuron transistor is developed using the neuroscience approach for AGI applications. Neuronal behavior (“weighted sum and threshold” function) is based on the complementary metal-oxide-semiconductor (CMOS) negative differential resistance (NDR) theory. The neuron transistor is implemented by the UMC 180-nm commercial standard CMOS process, which is beneficial to implement an entire neural network or integrate with other CMOS circuits on the same chip. The neuron transistor is composed of three inputs V_g1, V_g2, and V_g3 and a control terminal, V_con, a load terminal, V_b(load), and a driver terminal, V_b(driver) respectively. The width of each input is 1.8 µm, and the inputs have 1, 2, and 4 fingers respectively, that is, the weight ratio is 1:2:4. V_b(load) and V_b(driver) enable a neuron transistor to function more closely resembles a real biological neuron, with improved sensitivity and less complexity comparing to a traditional artificial neural network. The neuron MOS transistor was measured at the maximum frequency of 10 kHz. It had an extremely low power consumption of <10^-4 µW and a miniscule footprint 30×15 µm². As the process feature size decreases, the chip’s operating frequency could be increased by one order of magnitude, while its power consumption and footprint will decrease.