TLC STT-MRAM aware LLC for multicore processor

抄録

Since state-of-the-art multicore processors that execute complicated applications demand a large last-level cache (LLC) for reducing memory latency, next-generation memories have being recently attracted great attentions. Triple-level cell (TLC) spin-transfer torque (STT)-magnetic random access memories (MRAMs) provide high storage density, but degrade latency and power consumption due to three-step resistance state transition and detection processes for write and read operations, respectively. In this paper, we propose a TLC STT-MRAMs aware LLC that limit such penalties for multicore processors. Our LLC minimizes the occurrence of three-step resistance state transition and detection processes via the proposed cell division mapping and conditional block swapping techniques. Experimental results show that the proposed LLC achieves on average 17.2% higher performance and 17.9% lower power consumption than conventional LLCs comprised of TLC STT-MRAMs.