Embedded multiport data buffer for a solid-state drive controller

Abstract

Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today’s standards; however, they are small, low cost and consume little power. SSD controllers are thus designed as DRAM-less chips. SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port. In an SSD controller, more than two IPs simultaneously access the same SRAM, such as the CPU, data interface, and multiflash memory channel. It is thus complicated to exchange data between multiple ports. A new architecture of the multi-port data buffer (M-Buffer) is proposed in this study to solve this problem. M-Buffer is composed of wide SRAM, a smart arbitrator and several interface port logics. The M-Buffer can be designed as a reusable architecture and is small, low cost and consumes little power.