A multi-level architecture for hardware Trojan and vulnerability runtime detection and response towards cryptographic IP

Abstract

Existing functional validation approaches and post-manufacturing tests are inadequate to detect all hardware bugs and hardware Trojans in third-party intellectual property blocks (3PIPs). Especially for cryptographic IPs, a well-designed framework is needed for detecting and mitigating hardware security risks even after chip deployment. In this paper, we present an innovative multi-level architecture providing runtime hardware security detection and response. The proposed architecture consists of a controller and a security wrapper, enabling the collaborative operation of three different types of detection and three levels of response according to the potential malicious impact. We show that a field programmable gate array prototype of the proposed architecture can pursue 4 hardware bug and 6 hardware Trojan detection towards an AES IP, and make appropriate protective responses.