A fully integrated CMOS RC oscillator is presented. The oscillator is inverter-based. An adaptive body biasing (ABB) scheme is proposed to regulate the trip point of the decision inverter adaptively, thus alleviating the frequency variation over PVT. To achieve low power consumption all components are in the sub-threshold region. The circuit is designed in a 55-nm CMOS process with an area of 0.052mm². The simulation result shows a temperature sensitivity of 59ppm/°C from -40∼125°C which achieves a 72ppm/°C reduction as compared to an oscillator without ABB. the oscillator operates at 33kHz and consumes 183nW from a 0.6V supply.

External capacitors in conventional LDO regulators can reduce transient response characteristics such as overshoot and undershoot. However, the capacitor-less LDO regulator proposed in this study achieves the transient response improved by applying body technique to the pass transistor, thereby provides the high areal efficiency and excellent current driving capability, and shows the improved ESD robustness characteristics. Also, the proposed ESD protection device based on due to the SCR (Silicon Control Rectifier) built into the output node and the power line. As a result, it was confirmed that the transient response characteristics of the proposed LDO regulator were improved and free space could be secured by applying the body technique of the pass transistor. The operating conditions of the proposed LDO regulator were set as an input voltage varying from 3.3V to 4.5V, a maximum load current of 200mA, and the output voltage of 3V. As a result of the measurement, when the load current was 200mA, the voltage was found to be 23mV in the undershoot state and 29mV in the overshoot state. In addition, the ESD robustness characteristic of HBM is secured at 8kV or higher.

A four-quadrant analog multiplier with ultra-low supply voltage operation, rail-to-rail input swing and insensitive to different dc levels between the multiplied input signals is presented. It is based on the Floating-Bulk technique, in which the input signal is coupled to the bulk terminal of a PMOS transistor by means of an input capacitor. This allows rail-to-rail operation and eliminates the dc level of the input signals regardless of the offset between them, maintaining linearity. Moreover, it also eliminates the threshold-voltage requirement in the signal path of the input transistors, allowing very low voltage operation defined by a gate-source and a drain-source voltages. Experimental results in 0.5µm technology demonstrate rail-to-rail operation with a 1.1V supply voltage even with different dc level voltages between the multiplied input signals. It offers a distortion of THD =0.95% for an input signal of 0.2V_pp at 100kHz.

In this paper, a low delay circuit structure is proposed for composite field S-box circuit. In the low delay structure, the multiplications over GF((2²)²) are constructed by XOR-AND-XOR-networks, and the multiplicative inverse over GF((2²)²) are constructed by AND-XOR-networks. As XOR-networks are linear operations, they can be further expressed as constant matrix multiplications. In this paper, the adjacent matrix multiplications in S-box are merged to reduce the delay. Compared with previous works, our S-box implementations have lower delay.

Arc faults in power systems may cause significant damage to equipment and even lead to electrical fires and hazard for personnel if they are not detected and isolated promptly. The series arc fault in a distribution system can be more dangerous compared to the parallel arc fault, because its low fault current will hinder the circuit breakers from responding in a timely manner. Therefore, it is necessary to properly detect the series arc fault. In this paper, a system-on-chip (SoC) for series AC arc fault acquisition is presented, which is based on two channels of configurable sampling rate successive approximation register (SAR) analog-to-digital-converters (ADCs). As the arc faults with different loads have different characteristics and may need a higher sampling rate under some circumstances, the adjustable sampling rate can meet varying needs. The system is implemented using a 55nm CMOS process with a die area of 4.683mm² and power dissipation of 75.9mW. The proposed SAR ADC design can achieve a good Schreier figure-of-merit (FoM) of 161dB at 1MS/s sampling rate. With this ADC design, the SoC can complete arc faults acquisition with high precision and configurable sampling rate at a low cost. Meanwhile, the system can sample voltage and current signals from the smart grid respectively to initially locate the arc fault.

Existing functional validation approaches and post-manufacturing tests are inadequate to detect all hardware bugs and hardware Trojans in third-party intellectual property blocks (3PIPs). Especially for cryptographic IPs, a well-designed framework is needed for detecting and mitigating hardware security risks even after chip deployment. In this paper, we present an innovative multi-level architecture providing runtime hardware security detection and response. The proposed architecture consists of a controller and a security wrapper, enabling the collaborative operation of three different types of detection and three levels of response according to the potential malicious impact. We show that a field programmable gate array prototype of the proposed architecture can pursue 4 hardware bug and 6 hardware Trojan detection towards an AES IP, and make appropriate protective responses.

This paper presents a process, voltage, and temperature (PVT)-insensitive high dynamic range output stage for switched-capacitor (SC) circuits. A new technique of constant threshold voltages using bulk voltages adjustment is presented to realize the output stage with the N and P-type (N-P) complementary transistors. Boosting circuits are used to generate bulk voltages higher than the supply voltage or lower than the ground voltage. The stability of the bulk loop consisting of a boosting circuit, an amplifier, and a replica transistor is studied. This design is implemented in TSMC 0.18µm technology. Simulation results show that the output stage can achieve a differential dynamic range of 2.5Vpp, obtaining a significant 47% improvement.