Design of capless LDO regulator with low voltage application based ESD protection circuit using SR-latch switch structure

Abstract

The transient response characteristics such as overshoot and undershoot can be affected by the external capacitors of the LDO regulator. However, the capacitor-less LDO regulator proposed in this paper has an SR-Latch switch structure applied to the output terminal and gate terminal of the pass transistor in order to achieve improved transient response and secure excellent current driving capability. In addition, the proposed ESD protection device uses Penta-Well in low voltage applications embedded in the output stage and power line based on SCR (Silicon Control Rectifier) to provide improved ESD robustness characteristics. As a result, the transient response characteristics of the proposed LDO regulator with the SR-Latch switch structure were improved and the quiescent current was secured. The operating conditions of the proposed LDO regulator with the SR-Latch switch structure were set to an input voltage of 3.3V to 4.5V, maximum load current of 250mA, and an output voltage of 3V. As a result of the measurement, it was confirmed that the proposed LDO regulator maintained an undershoot voltage of 42mV and an overshoot voltage of 31mV when a load current of 250mA was applied. In addition, HBM ESD robustness is guaranteed at 6kV.